1. Technical Field
The present invention relates to partial reconfiguration of Field Programmable Gate Arrays (FPGAs). More particularly, the present invention relates to a method for dynamic partial reconfiguration to relocate logic performing some functions while logic performing other functions remains static in the FPGA.
2. Related Art
FPGAs supporting dynamic partial reconfiguration are emerging as a standard to support applications that require low power use and have a subset of features or functions to be implemented at any given time. By using FPGAs supporting dynamic partial reconfiguration, a design may be implemented with fewer devices (FPGAs) thus reducing power requirements. For certain applications the designer may wish to implement functions so that they can be moved or reprogrammed into different parts of the device.
For reference, a block diagram of components of a conventional FPGA is shown in FIG. 1. The FPGA includes input/output (I/O) blocks 2 (each labeled 10) located around the perimeter of the FPGA, multi-gigabit transceivers (MGT) 4 interspersed with the I/O blocks 2, configurable logic blocks 6 (each labeled CLB) arranged in an array, block random access memory 8 (each labeled BRAM) interspersed with the CLBs, configuration logic 12, configuration interface 14, on-chip processor 16 and an internal configuration access port (ICAP) 15. The FPGA also includes other elements, such as a programmable interconnect structure (not shown) and a configuration memory array 17. Although FIG. 1 shows a relatively small number of I/O blocks 2, CLBs 6 and block RAMs 8 for illustration purposes, it is understood that an FPGA typically includes many more of these elements.
The FPGA of FIG. 1 is programmed or configured in response to a set of configuration data values that are loaded into a configuration memory array 17 of the FPGA from an external PROM store (not shown) via configuration interface 14 and configuration logic 12. The configuration interface 14 can be, for example, a parallel select map interface, a JTAG interface, or a master-serial interface. The configuration memory array 17 can be visualized as a rectangular array of bits. The bits are grouped into frames that are one-bit wide words that extend in columns from the top of the array to the bottom. The configuration data values are typically loaded into the configuration memory array one frame at a time from the external store via the configuration interface 14.
More efficient reconfiguration of an FPGA is performed by only rewriting a portion of the frames or columns in the configuration memory array 17 using partial reconfiguration. In one reconfiguration method, the ICAP 15 is used to rewrite data in the configuration memory array 17 in order to generate or instantiate the FPGA's internal logic (e.g., CLBs 6 and BRAMs 8). In other words, one part of the configured FPGA can reconfigure another part of the FPGA. Without using the ICAP 15, reconfiguration can also be performed by loading reconfiguration frames through the configuration interface 14 using external customized logic components to over-write frame data in the configuration memory array 17.
In order to provide for efficient partial reconfiguration, a circuit arrangement shown in FIG. 2 can be provided. To control reading and writing of data into the configuration memory array 17 of an FPGA, a controller 20 is used. The controller 20 can be the ICAP 15 located internal to the FPGA, or alternatively the controller 20 can also be provided outside the FPGA. To mirror data in the configuration memory array 17, configuration store 22 is used. The configuration store 22 is typically a PROM or other non-volatile memory device. The configuration store 22 can speed read and write operations because a bottleneck is otherwise typically created through the configuration interface 14 to the configuration memory array 17. With the configuration store 22 used, data is first modified in the configuration store 22 and later loaded into the configuration memory array 17 through the configuration interface 14 in a frame-by-frame manner.
There are new applications emerging that are power and area sensitive that lend themselves to use FPGA devices supporting partial dynamic configuration. These new applications require that a large set of functions exist in the system and that the FPGA may implement a subset of these functions selectable by the user during operation of the FPGA. The methodology to implement this has been to identify areas on the FPGA to be used as the reconfiguration areas for the designs to be dynamically swapped in and then to implement each of the functions in, the different locations identified.
In one example illustrated in FIG. 3, a design using dynamic reconfiguration includes four areas 51-54 in which any of twenty functions to run at any time are identified. In order to do this the designer would identify the four areas 51-54 on the FPGA and reserve the area for the reconfigurable designs. Then the twenty different functions could be selectively implemented in the areas 51-54. If the designer wanted particular functions to be implemented in the four areas, then the functions could be implemented using the place and route tools into each of the four areas. In this example there are twenty functions and four different physical locations on the device the designer would implement 80 different designs for full cross-location capability. The eighty designs would be used to generate eighty different bit streams for programming and these would be held in PROMs on the product to be used to program the different areas as required.
It would be desirable from a power and PROM use point of view to be able to minimize PROM storage and power required to be able to move functions from one area to another. Significant PROM space is needed to store large portions of the frame data needed to move functions from one FPGA area to another. Likewise, significant power is needed to generate voltages for reprogramming a large number of frame data into the configuration memory.